1. Field of the Invention
The invention relates to a method of fabricating a lateral MOS transistor, and more particularly to an improvement in ion-implantation to a channel region.
2. Description of the Related Art
In a conventional method of fabricating a lateral MOS transistor, thermal annealing is carried out at a high temperature and for a long period of time for obtaining desired channel length and breakdown voltage, after impurities have been implanted into a substrate. FIGS. 1A to 1E are cross-sectional views of a MOS transistor, illustrating respective steps of a conventional method of fabricating the same. As an example, FIGS. 1A to 1E illustrates a method of fabricating an n-channel lateral MOS transistor.
As illustrated in FIG. 1A, a p-type silicon substrate 101 is implanted at a dose of 1.times.10.sup.13 cm.sup.-2 to 3.times.10.sup.13 cm.sup.-2 phosphorus (P), followed by thermal annealing at 1000.degree. C. to 1200.degree. C. for 8 to 12 hours to thereby form an n-type well region 102 in the p-type silicon substrate 101. Then, there are formed device isolation oxide films 103 by local oxidation of silicon (LOCOS), followed by thermal oxidation at 1000.degree. C. to 1200.degree. C. for about 5 to 20 minutes in O.sub.2 atmosphere to thereby form a gate oxide 104 film on the silicon substrate 101. The gate oxide film 104 has a thickness in the range of 150 to 400 angstroms. Then, polysilicon is deposited over the gate oxide film 104. The polysilicon is etched so as to leave a selected region unetched by photolithography, to thereby form a gate electrode 105 on the gate oxide film 104.
Then, photoresist is deposited over a resultant, and etched so as to leave a selected region unetched. Thus, there is formed a photoresist mask 106 which covers a region other than a region where a channel region is to be formed, as illustrated in FIG. 1B.
Then, the p-type silicon substrate 101 is ion-implanted at an accelerating voltage of 50 to 80 KeV at a dose of 3.times.10.sup.13 cm.sup.-2 to 5.times.10.sup.13 cm.sup.-2 boron (B), followed by thermal annealing at a high temperature for a long period of time, specifically, at 1000.degree. C. to 1200.degree. C. for about 50 to 80 minutes, to thereby activate and diffuse boron having been ion-implanted into the silicon substrate 101. Thus, a p-type channel region 107 is formed in the n-type well region 102, as illustrated in FIG. 1C.
Then, as illustrated in FIG. 1D, after the photoresist mask 106 has been removed, the p-type silicon substrate 101 is ion-implanted at 80 to 160 KeV at a dose of 5.times.10.sup.15 cm.sup.-2 to 1.times.10.sup.16 cm.sup.-2 arsenic (As) or phosphorus (P), employing the gate electrode 105 as a mask in a self-aligned manner. Thus, there are formed n-type diffusion layers around the gate electrode 105, which diffusion layers act as a drain region 108 and a source region 109. Thus, the channel region 107, the drain region 108, the source region 109, and the gate electrode 105 cooperate with each other to thereby form a lateral MOS transistor.
Then, as illustrated in FIG. 1E, there is formed an interlayer insulating film 110 having a thickness of about 1.0 .mu.m over a resultant by CVD. Then, contact holes are formed through the interlayer insulating film 110 to the drain and source regions 108 and 109. Then, an aluminum film is formed by sputtering over the interlayer insulating film 110, and is etched in selected regions to thereby form drain and source electrodes 111. Then, a passivation film 112 is formed covering a resultant.
As mentioned above, when the channel region 107 is to be formed in the conventional process, the silicon substrate 101 is ion-implanted with impurities, followed by thermal annealing to thereby cause the channel region 107 to thermally diffuse to a region just below the gate electrode 105. Thus, thermal annealing at a high temperature for a long period of time, specifically, at 1000.degree. C. to 1200.degree. C. for about an hour, was carried out in the conventional process to horizontally diffuse the impurities to a region just below the gate electrode 105.
FIG. 2 illustrates an impurities-profile in the channel region 107. As illustrated, the thermal annealing at a high temperature for a long period of time causes the impurities profile to be gently sloping in a region located just below the gate electrode 105. The gently sloped impurities-profile causes a depletion layer to expand in the region located just below the gate electrode 105, causing punch through to readily occur. In addition, the thermal annealing at a high temperature for a long period of time also causes impurity layers formed in other devices to thermally diffuse. The performances of 0.5 .mu.m design-rule devices are in particular deteriorated. Hence, it was quite difficult in the conventional method of fabricating MOS transistor to fabricate a semiconductor integrated circuit device including a plurality of fine devices in a common substrate.
Further, DSA (diffusion self-aligned) MOS transistor is described in "Device Basic Technology" at the sub-section 8-4-2. According to the description, it would be possible to fabricate depletion type MOS transistor on a common semiconductor substrate, since a highly resistive substrate is employed.